module data_mem_top_tb ();
  
  reg clk,rst,MemWrite,MemRead;
  reg [7:0] DataAddress,DataWrite;
  
  wire [7:0] ReadData;

data_mem_top U1(clk,rst,DataAddress,DataWrite,MemWrite,MemRead,ReadData);

  // initial #200 $finish;
    initial begin
    clk=1;  
    rst=0; 
    MemWrite=0;
    MemRead=0;
    forever #10 clk=~clk; 
    end 
    
    initial begin    
    #20;
    MemWrite = 1; DataAddress = 8'b00000000; DataWrite = 8'b11111111; #20;
    
    DataAddress = 8'b00000100; DataWrite = 8'b11111110; #20;
   
    DataAddress = 8'b00001000; DataWrite = 8'b11111100; #20;
   
    DataAddress = 8'b00001100; DataWrite = 8'b11111000; #20;
   
    MemWrite = 0; MemRead =1; DataAddress = 8'b00000000; #20;
   
    DataAddress = 8'b00000100; #20;
   
    DataAddress = 8'b00001000; #20;
   
    DataAddress = 8'b00001100; #20;

    $stop;
  end

  endmodule
    
